Analyze coverage reports, classify gaps, and propose targeted stimulus or model fixes with plateau detection.

Review architecture and specification views before RTL work begins, then classify the project as ready, risky, or blocked.

Generate synthesizable RTL modules from architecture notes, interface tables, register maps, and timing constraints.

Review timing, equivalence, lint, CDC, and DRC/LVS summaries and prepare an auditable release note.

Build UVM agents, sequence skeletons, scoreboards, and smoke tests from a verified interface contract.

Detect local EDA project structure, prepare repeatable commands, and coordinate compile, simulation, regression, and triage loops.

Produce synthesis setup notes, initial SDC constraints, and QoR review tasks from architecture and timing intent.

Check whether RTL, constraints, floorplan inputs, and signoff assumptions are ready for physical implementation.